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Memory architecture
Results: 1714

#	Item
801	DeAliaser: Alias Speculation Using Atomic Region Support Wonsun Ahn Yuelu Duan Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:16 Software engineering Programming language implementation Central processing unit Computer memory Compiler construction Alias analysis CPU cache Loop unwinding Linearizability Computing Computer architecture Compiler optimizations
802	do i:[removed][removed] Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-26 23:39:42 Central processing unit Parallel computing Chunk Process CPU cache Computer architecture Computing Computer hardware Computer memory
803	Encyclopedia of Parallel Computing “00166” — [removed] — 14:04 — Page 1 — #2 C  Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-05-19 11:47:48 Parallel computing Non-Uniform Memory Access Cache-only memory architecture CPU cache Memory architecture Uniform memory access Kendall Square Research Cache Random-access memory Computing Computer memory Concurrent computing
804	Muen - Toolchain Reto Buerki Adrian-Ken Rueegsegger October 7, 2014 Add to Reading List Source URL: muen.codelabs.ch Language: English - Date: 2014-10-07 16:56:20 Linux Kernel Linux kernel Thread Unix C dynamic memory allocation Virtual memory Debian Software Computer architecture System software
805	L1 Data Cache Decomposition for Energy Efficiency Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 11:58:14 Cache CPU cache Computer architecture Computing R10000 Computer hardware Central processing unit Computer memory
806	Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA E Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-08-13 13:31:19 Computer memory Computer hardware CPU cache Central processing unit Instruction set architectures Cache algorithms Memory hierarchy Blue Gene Xeon Computer architecture Computing Cache
807	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-01-15 09:17:36 MIPS architecture Ring Instruction set Capability-based security 64-bit Hypervisor Kernel Reduced instruction set computing Memory protection Computer architecture Central processing unit Instruction set architectures
808	src/sys/i386/i386/machdep Add to Reading List Source URL: vidstrom.net Language: English - Date: 2004-06-17 12:11:45 C programming language Interrupts C++ POSIX System call Interrupt descriptor table INT Exit X86 memory segmentation Computer architecture Computing X86 architecture
809	Wshp. on Memory Performance Issues, Intl. Symp. on Computer Architecture, June[removed]Speculative Locks for Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors Jose´ F. Mart´ınez and Josep Torre Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-12-19 18:12:59 Computer hardware Central processing unit Threads Microprocessors Lock Non-blocking algorithm Simultaneous multithreading Parallel computing Critical section Concurrency control Computing Computer architecture
810	Characterizing the Impact of End-System Affinities On the End-to-End Performance of High-Speed Flows Nathan Hanford1 , Vishal Ahuja1 , Mehmet Balman2 , Matthew K. Farrens1 , Dipak Ghosal1 , Eric Pouyoul2 and Brian Tierne Add to Reading List Source URL: www.es.net Language: English - Date: 2014-12-11 12:32:11 Computer memory Scheduling algorithms Microprocessors Computer architecture Multi-core processor Parallel computing AMD 10h Jumbo frame CPU cache Computing Computer hardware Concurrent computing

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